The RSX II processor is a highly pipelined RISC design, which requires only one CPU execution cycle for most instructions. It achieves much of its speed from multiple independent functional units capable of operating in parallel during multi-cycle instructions (Figure 1). This is implemented using 1 micron CMOS chip technology and a complement of cell-based and semi-custom application specific integrated circuits (ASICs) to create the dual mode environments. The dual independent 64-bit data paths (128 bits total) tomemory and highly paralleled RISC design yield a system capable of achieving one cycle per instruction execution. Dual, independent 28-bit address paths (56 bits total) are provided between the processor and memory. The Execution Unit and the Instruction Unit each have access to both the data and address paths. The parallel execution of integer and floating point operations contribute to this high execution rate. Innovative superscalar floating point can initiate two floating point operations in one CPU cycle, thus making the system ideally suited for demanding scientific environments.
The local memory bus provides a private path between the processor and memory system. Its 213 MB per second bandwidth easily sustains the high processing rates of the RISC mode. It is complemented by an independent real-time I/0 bus that does not interfere with the CPU access to memory. The memory system is quad-ported to achieve parallel throughput of real-time I/0 streams into memory without stealing any cycles from the CPU. One of the four memory ports is utilized by COMPRO's Reflective Memory System (RMS) that permits connectivity of multiple systems.
Floating point architecture is one of RSX II's more innovative attributes. It is built upon a multiply-accumulate function that executes two floating point operations in one instruction. Among these instruction pairs are multiply-add, multiply-subtract, divide-add, divide-subtract and others. This results in extremely high processing rates for floating point intensive applications such as many forms of simulation. Also, certain mathematical sequences such as polynomial evaluation (cumulative multiply-add sequences) are accelerated. RSX II boasts of one to two microsecond intrinsic (SINE, COSINE, etc.) due to these powerful floating point features.
Large Cache Memory Design - (Purchased Separately)
The direct mapped design permits a simplified model for multi-CPU cache coherency and non-intrusive real time I/0. The DMC is quad-ported and operates at an aggregate rate of over 290 MB per second across all ports. Two ports are for the CPU, one port is for the real-time I/0 bus, and one port is for RMS. Any updates to the DMC occur in one cycle whether from the RMS port, I/0 port, or CPU. This permits very deterministic system design of multiple computers with simultaneous I/0 without impacting CPU performance.
By making the DMC the master interface for all memory access, cache coherency is ensured. All CPU references to main memory filter through the DMC (Figure 2). If the CPU requests data from addresses outside those in the DMC, the DMC issues the requests to main memory. Direct mapping into contiguous address ranges eliminates the need for cache flushing and duplication of cache addresses with main memory addresses. The CPU views DMC memory as main memory and there are no 'cache write-throughs' (except for RMS which does 'reflect' memory writes across the RMS bus). COMPRO's RSX II operating systems include software tools that enable you to distribute portions of tasks between DMC addresses and main memory addresses. In real-time environments, this provides optimum user control. Regardless of simultaneous 1/0 traffic or multiprocessor load, RSX II delivers performance to an unprecedented degree for RISC systems. Cache 'miss' and 'flush' problems are virtually eliminated.
There are a host of languages that track industry standards such as Ada . FORTRAN, and C. All COMPRO systems are committed to full POSIX® compliance and COMPRO RSX II is no exception.
Separate Real-Time I/0 Bus
The RSX II real-time I/0 bus is based on COMPRO's pre-emptible SeIBUS™ , which can interleave prioritized packets of smaller transfers among larger transfers. This means there is no real performance penalty due to larger transfers 'hogging' the bus for an entire transmission. Smaller real-time bursts can always interleave with the larger transfers. This type of I/0 available on RSX II is atypical of most RISC systems and more typical of mainframe-style channel I/0.
The entire above-mentioned activity can occur without significantly impacting CPU performance. In fact, all 26 MB of I/O bandwidth can be saturated without significantly slowing down the CPU due to the very high aggregate throughput of the multi-ported DMC.
An additional I/O capability is realized when using the RMS port into the DMC as an I/0 channel. Over 53 MB per second of I/0 is available through RMS to supplement the 26 MB of real-time I/0 through the real-time I/O bus. This gives an aggregate of over 79 MB of I/O into the DMC without cache coherency problems and without significantly impacting CPU performance.
For CONCEPT/32 users. RSX II CPUs can be installed in existing SelCONNECTION™ cabinets to provide easy upgrades from MULTISel™ to RSX II RISC systems.
Special Real-Time Features
User tasks have access to eight externally connected traps. These external traps require less than five-microsecond latency to get to the first instruction in the trap handler. Each of the external trap lines has a dedicated memory location associated with it. This dedicated memory location stores the starting address of the trap service routine for that particular trap. The priorities associated with these external traps are higher than external interrupts, but lower than system integrity for traps.
The CPU includes eight internal timers that can be used by both the operating system and the user's tasks and offers a range of resolutions up to 75 nanoseconds. One interval timer is privileged (for operating system use) and can be stopped, started, loaded, and examined. This programmable 32-bit interval timer can be used to generate interrupts at prescribed intervals from 150 nanoseconds and up. The other interval timers have extended features to act as privileged I/0 interrupting timers or as non-interrupt unprivileged register access timers.
A clock-calendar function provides modifiable date and time-of-day with seconds resolution and continues to run when the system is powered off.
CONCEPT/32 Compatibility Mode
There are many native mode features that can be used. Over time, after moving applications to RSX II compatibility mode including expanded logical address space. Demand paging, IEEE-754 floating point, directly vectored SVCs, and more. RSX II makes it possible to transition to as few or as many of these native mode features as desired. If compatibility mode is sufficient for some tasks, they need not be changed. As the applications demand or on an as-needed basis, some tasks can begin to take advantage of native mode features while other tasks are running in compatibility mode. This convenience eliminates the high cost of conversion and eases the transition of applications to the features and benefits of RSX II RISC technologies.
Corequisite: DMC and 4 or 16 MB SRAM
Prerequisite: 4841D or 4844A
Corequisite: DMC and 4 or 16 MB SRAM
Prerequisite: 1965-PC-System (not required if being used to expand existing 6841 system)
Corequisite: DMC and 4 or 16 MB SRAM
Prerequisite: 1965-PC System (if being used as host).
Co-requisite: DMC and 4 or 16 MB SRAM
Suffix Modifier: 4633-ab
Memory Options (Remanufactured):
R3031-0(0/1/2/3/4/5) - 16 MB SRAM, 75 ns
RSX II, MULTISel and SelCONNECTION are trademarks of COMPRO, CONCEPT/32 is a registered trademark of COMPRO, POSIX is a registered trademark of IEEE.